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uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/modelsim/AND2Gate_modelsim.xrf

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LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:32 +00:00
vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd
LSD: aula01 part2 finished
2023-03-01 12:17:08 +00:00
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd
LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:32 +00:00
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.cbx.xml
design_name = hard_block
design_name = GateDemo
instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
instance = comp, \LEDR[1]~output\, LEDR[1]~output, GateDemo, 1
instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
LSD: aula01 part2 finished
2023-03-01 12:17:08 +00:00
instance = comp, \system_core|and_gate|outPort\, system_core|and_gate|outPort, GateDemo, 1