181 lines
1.9 KiB
Plaintext
181 lines
1.9 KiB
Plaintext
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$comment
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File created using the following command:
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vcd file LogicDemo.msim.vcd -direction
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$end
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$date
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Tue Mar 7 20:45:48 2023
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$end
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$version
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ModelSim Version 2020.1
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$end
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$timescale
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1ps
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$end
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$scope module logictop_vhd_vec_tst $end
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$var wire 1 ! LEDR [5] $end
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$var wire 1 " LEDR [4] $end
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$var wire 1 # LEDR [3] $end
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$var wire 1 $ LEDR [2] $end
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$var wire 1 % LEDR [1] $end
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$var wire 1 & LEDR [0] $end
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$var wire 1 ' SW [1] $end
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$var wire 1 ( SW [0] $end
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$scope module i1 $end
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$var wire 1 ) gnd $end
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$var wire 1 * vcc $end
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$var wire 1 + unknown $end
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$var wire 1 , devoe $end
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$var wire 1 - devclrn $end
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$var wire 1 . devpor $end
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$var wire 1 / ww_devoe $end
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$var wire 1 0 ww_devclrn $end
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$var wire 1 1 ww_devpor $end
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$var wire 1 2 ww_LEDR [5] $end
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$var wire 1 3 ww_LEDR [4] $end
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$var wire 1 4 ww_LEDR [3] $end
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$var wire 1 5 ww_LEDR [2] $end
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$var wire 1 6 ww_LEDR [1] $end
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$var wire 1 7 ww_LEDR [0] $end
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$var wire 1 8 ww_SW [1] $end
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$var wire 1 9 ww_SW [0] $end
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$var wire 1 : \LEDR[5]~output_o\ $end
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$var wire 1 ; \LEDR[4]~output_o\ $end
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$var wire 1 < \LEDR[3]~output_o\ $end
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$var wire 1 = \LEDR[2]~output_o\ $end
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$var wire 1 > \LEDR[1]~output_o\ $end
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$var wire 1 ? \LEDR[0]~output_o\ $end
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$var wire 1 @ \SW[1]~input_o\ $end
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$var wire 1 A \SW[0]~input_o\ $end
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$var wire 1 B \inst|norOut~0_combout\ $end
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$var wire 1 C \inst|nandOut~0_combout\ $end
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$var wire 1 D \inst|xorOut~combout\ $end
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$var wire 1 E \ALT_INV_SW[0]~input_o\ $end
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$var wire 1 F \inst|ALT_INV_nandOut~0_combout\ $end
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$var wire 1 G \inst|ALT_INV_norOut~0_combout\ $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0)
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1*
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x+
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1,
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1-
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1.
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1/
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10
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11
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1:
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1;
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0<
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0=
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0>
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1?
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0@
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0A
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0B
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0C
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0D
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1E
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1F
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1G
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0'
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0(
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12
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13
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04
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05
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06
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17
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08
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09
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1!
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1"
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0#
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0$
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0%
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1&
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$end
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#200000
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1(
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19
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1A
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0E
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1B
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1D
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0G
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0?
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1<
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1=
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07
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0:
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14
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15
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0&
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02
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1$
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1#
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0!
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#400000
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0(
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1'
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09
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18
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1@
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0A
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1E
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1?
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17
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1&
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#600000
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1(
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19
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1A
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0E
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1C
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0D
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0F
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0?
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0<
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1>
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07
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0;
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04
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16
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0&
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03
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1%
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0#
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0"
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#800000
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0(
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0'
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09
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08
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0@
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0A
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1E
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0B
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0C
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1F
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1G
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1?
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0>
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0=
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17
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1:
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1;
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06
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05
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1&
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12
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13
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0%
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0$
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1"
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1!
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#1000000
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