33 lines
865 B
VHDL
33 lines
865 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity FreqDivider is
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port (clkIn : in std_logic;
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clkOut : out std_logic
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);
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end FreqDivider;
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architecture Behavioral of FreqDivider is
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signal s_counter : unsigned(31 downto 0);
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signal s_halfWay : unsigned(31 downto 0);
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signal k : std_logic_vector(31 downto 0);
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begin
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k <= x"01AD7840";
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s_halfWay <= unsigned(k);
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process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_counter = s_halfWay - 1) then
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clkOut <= '0';
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s_counter <= (others => '0');
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else
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if (s_counter = s_halfWay/2 - 1) then
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clkOut <= '1';
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end if;
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s_counter <= s_counter + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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