119 lines
3.1 KiB
Plaintext
119 lines
3.1 KiB
Plaintext
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "11/04/2022 12:48:42"
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-- Vhdl Test Bench(with test vectors) for design : Dec2_4
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY Dec2_4_vhd_vec_tst IS
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END Dec2_4_vhd_vec_tst;
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ARCHITECTURE Dec2_4_arch OF Dec2_4_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL E0L : STD_LOGIC;
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SIGNAL E1 : STD_LOGIC;
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SIGNAL X0 : STD_LOGIC;
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SIGNAL X1 : STD_LOGIC;
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SIGNAL Y0 : STD_LOGIC;
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SIGNAL Y1 : STD_LOGIC;
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SIGNAL Y2 : STD_LOGIC;
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SIGNAL Y3 : STD_LOGIC;
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COMPONENT Dec2_4
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PORT (
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E0L : IN STD_LOGIC;
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E1 : IN STD_LOGIC;
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X0 : IN STD_LOGIC;
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X1 : IN STD_LOGIC;
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Y0 : OUT STD_LOGIC;
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Y1 : OUT STD_LOGIC;
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Y2 : OUT STD_LOGIC;
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Y3 : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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i1 : Dec2_4
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PORT MAP (
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-- list connections between master ports and signals
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E0L => E0L,
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E1 => E1,
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X0 => X0,
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X1 => X1,
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Y0 => Y0,
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Y1 => Y1,
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Y2 => Y2,
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Y3 => Y3
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);
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-- E0L
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t_prcs_E0L: PROCESS
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BEGIN
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LOOP
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E0L <= '0';
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WAIT FOR 100000 ps;
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E0L <= '1';
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WAIT FOR 100000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_E0L;
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-- E1
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t_prcs_E1: PROCESS
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BEGIN
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LOOP
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E1 <= '0';
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WAIT FOR 50000 ps;
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E1 <= '1';
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WAIT FOR 50000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_E1;
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-- X1
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t_prcs_X1: PROCESS
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BEGIN
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LOOP
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X1 <= '0';
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WAIT FOR 25000 ps;
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X1 <= '1';
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WAIT FOR 25000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_X1;
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-- X0
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t_prcs_X0: PROCESS
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BEGIN
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LOOP
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X0 <= '0';
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WAIT FOR 12500 ps;
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X0 <= '1';
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WAIT FOR 12500 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_X0;
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END Dec2_4_arch;
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