2023-01-11 18:07:46 +00:00
Timing Analyzer report for MuxDemo
2023-01-25 23:45:44 +00:00
Wed Jan 25 23:41:57 2023
2023-01-11 18:07:46 +00:00
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1200mV 85C Model Setup Summary
8. Slow 1200mV 85C Model Hold Summary
9. Slow 1200mV 85C Model Recovery Summary
10. Slow 1200mV 85C Model Removal Summary
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
12. Slow 1200mV 85C Model Metastability Summary
13. Slow 1200mV 0C Model Fmax Summary
14. Slow 1200mV 0C Model Setup Summary
15. Slow 1200mV 0C Model Hold Summary
16. Slow 1200mV 0C Model Recovery Summary
17. Slow 1200mV 0C Model Removal Summary
18. Slow 1200mV 0C Model Minimum Pulse Width Summary
19. Slow 1200mV 0C Model Metastability Summary
20. Fast 1200mV 0C Model Setup Summary
21. Fast 1200mV 0C Model Hold Summary
22. Fast 1200mV 0C Model Recovery Summary
23. Fast 1200mV 0C Model Removal Summary
24. Fast 1200mV 0C Model Minimum Pulse Width Summary
25. Fast 1200mV 0C Model Metastability Summary
26. Multicorner Timing Analysis Summary
27. Board Trace Model Assignments
28. Input Transition Times
29. Signal Integrity Metrics (Slow 1200mv 0c Model)
30. Signal Integrity Metrics (Slow 1200mv 85c Model)
31. Signal Integrity Metrics (Fast 1200mv 0c Model)
32. Clock Transfers
33. Report TCCS
34. Report RSKM
35. Unconstrained Paths Summary
36. Unconstrained Input Ports
37. Unconstrained Output Ports
38. Unconstrained Input Ports
39. Unconstrained Output Ports
40. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; MuxDemo ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE6E22C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
2023-01-25 23:45:44 +00:00
; Average used ; 1.01 ;
2023-01-11 18:07:46 +00:00
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
2023-01-25 23:45:44 +00:00
; Processors 2-4 ; 0.2% ;
2023-01-11 18:07:46 +00:00
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
2023-01-25 23:45:44 +00:00
; Y ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
2023-01-11 18:07:46 +00:00
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+----------------------------------------------------------------------------+
; Input Transition Times ;
+-------------------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; I10 ; 2.5 V ; 2000 ps ; 2000 ps ;
; Sel2 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I9 ; 2.5 V ; 2000 ps ; 2000 ps ;
; Sel1 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I8 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I11 ; 2.5 V ; 2000 ps ; 2000 ps ;
; Sel4 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I5 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I6 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I4 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I7 ; 2.5 V ; 2000 ps ; 2000 ps ;
; Sel3 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I2 ; 2.5 V ; 2000 ps ; 2000 ps ;
2023-01-25 23:45:44 +00:00
; I1 ; 2.5 V ; 2000 ps ; 2000 ps ;
2023-01-11 18:07:46 +00:00
; I0 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I3 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I13 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I14 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I12 ; 2.5 V ; 2000 ps ; 2000 ps ;
; I15 ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
+-------------------------+--------------+-----------------+-----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
2023-01-25 23:45:44 +00:00
; Y ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
2023-01-11 18:07:46 +00:00
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
2023-01-25 23:45:44 +00:00
; Y ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
2023-01-11 18:07:46 +00:00
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
2023-01-25 23:45:44 +00:00
; Y ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
2023-01-11 18:07:46 +00:00
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 20 ; 20 ;
; Unconstrained Input Port Paths ; 20 ; 20 ;
; Unconstrained Output Ports ; 1 ; 1 ;
; Unconstrained Output Port Paths ; 20 ; 20 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; I0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-25 23:45:44 +00:00
; I1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-11 18:07:46 +00:00
; I2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I3 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I4 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I5 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I6 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I7 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I8 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I9 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I10 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I11 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I12 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I13 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I14 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I15 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel3 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel4 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
2023-01-25 23:45:44 +00:00
; Y ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-11 18:07:46 +00:00
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; I0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-25 23:45:44 +00:00
; I1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-11 18:07:46 +00:00
; I2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I3 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I4 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I5 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I6 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I7 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I8 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I9 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I10 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I11 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I12 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I13 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I14 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; I15 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel2 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel3 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Sel4 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
2023-01-25 23:45:44 +00:00
; Y ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
2023-01-11 18:07:46 +00:00
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
2023-01-25 23:45:44 +00:00
Info: Processing started: Wed Jan 25 23:41:56 2023
2023-01-11 18:07:46 +00:00
Info: Command: quartus_sta MuxDemo -c MuxDemo
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'MuxDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 465 megabytes
2023-01-25 23:45:44 +00:00
Info: Processing ended: Wed Jan 25 23:41:57 2023
2023-01-11 18:07:46 +00:00
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
