101 lines
3.2 KiB
Plaintext
101 lines
3.2 KiB
Plaintext
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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(rect 16 16 112 208)
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(text "Teste1" (rect 5 0 43 15)(font "Intel Clear" (font_size 8)))
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(text "inst" (rect 8 175 28 188)(font "Intel Clear" ))
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(port
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(pt 0 32)
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(input)
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(text "S[2..0]" (rect 0 0 36 15)(font "Intel Clear" (font_size 8)))
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(line (pt 0 128)(pt 16 128))
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)
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(input)
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(text "X6" (rect 21 139 38 154)(font "Intel Clear" (font_size 8)))
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(line (pt 0 144)(pt 16 144))
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)
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(port
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(pt 0 160)
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(input)
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(text "X7" (rect 0 0 17 15)(font "Intel Clear" (font_size 8)))
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(line (pt 0 160)(pt 16 160))
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)
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(port
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(pt 96 32)
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(output)
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(text "Y" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
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(text "Y" (rect 66 27 75 42)(font "Intel Clear" (font_size 8)))
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(line (pt 96 32)(pt 80 32))
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)
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)
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)
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