39 lines
663 B
VHDL
39 lines
663 B
VHDL
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architecture Structural of Adder4 is
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signal intCarry : std_logic_vector(2 downto 0);
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begin
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bit0 : entity work.FullAdder(Behavioral) port map
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(
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a => a(0),
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b => b(0),
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cin => cin,
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s => s(0),
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cout => intCarry(0)
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);
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bit1 : entity work.FullAdder(Behavioral) port map
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(
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a => a(1),
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b => b(1),
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cin => intCarry(0),
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s => s(1),
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cout => intCarry(1)
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);
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bit2 : entity work.FullAdder(Behavioral) port map
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(
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a => a(2),
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b => b(2),
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cin => intCarry(1),
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s => s(2),
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cout => intCarry(2)
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);
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bit3 : entity work.FullAdder(Behavioral) port map
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(
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a => a(3),
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b => b(3),
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cin => intCarry(2),
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s => s(3),
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cout => cout
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);
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end Structural;
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