14 lines
6.5 KiB
Plaintext
14 lines
6.5 KiB
Plaintext
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678104305655 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678104305655 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 6 12:05:05 2023 " "Processing started: Mon Mar 6 12:05:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678104305655 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104305655 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop " "Command: quartus_map --read_settings_files=on --write_settings_files=off LogicDemo -c LogicTop" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104305655 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678104305778 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678104305778 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LogicUnit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file LogicUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LogicUnit-Behavioral " "Found design unit 1: LogicUnit-Behavioral" { } { { "LogicUnit.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310607 ""} { "Info" "ISGN_ENTITY_NAME" "1 LogicUnit " "Found entity 1: LogicUnit" { } { { "LogicUnit.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104310607 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LogicTop.bdf 1 1 " "Found 1 design units, including 1 entities, in source file LogicTop.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 LogicTop " "Found entity 1: LogicTop" { } { { "LogicTop.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678104310613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104310613 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "LogicTop " "Elaborating entity \"LogicTop\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678104310669 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LogicUnit LogicUnit:inst " "Elaborating entity \"LogicUnit\" for hierarchy \"LogicUnit:inst\"" { } { { "LogicTop.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf" { { 184 440 600 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678104310675 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678104311128 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678104311464 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678104311464 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678104311690 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678104311690 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678104311690 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678104311690 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 6 12:05:11 2023 " "Processing ended: Mon Mar 6 12:05:11 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678104311696 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678104311696 ""}
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