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uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.fit.qmsg

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[LSD] pratica01 part4 finished
2023-03-07 19:02:31 +00:00
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678212355649 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678212355649 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "EqCmpDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"EqCmpDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212355652 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678212355700 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678212355700 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678212356015 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678212356032 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678212356261 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "AUD_ADCDAT " "Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK2_50 " "Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK3_50 " "Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK_50 " "Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_INT_N " "Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_LINK100 " "Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_MDIO " "Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CLK " "Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_COL " "Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CRS " "Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[0\] " "Can't reserve pin ENET0_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[1\] " "Can't reserve pin ENET0_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[2\] " "Can't reserve pin ENET0_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[3\] " "Can't reserve pin ENET0_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DV " "Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_ER " "Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_TX_CLK " "Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_INT_N " "Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_LINK100 " "Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_MDIO " "Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CLK " "Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_COL " "Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CRS " "Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[0\] " "Can't reserve pin ENET1_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[1\] " "Can't reserve pin ENET1_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[2\] " "Can't reserve pin ENET1_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[3\] " "Can't reserve pin ENET1_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DV " "Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_ER " "Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_TX_CLK " "Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENETCLK_25 " "Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "FL_RY " "Can't reserve pin FL_RY -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "HSMC_CLKIN0 " "Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "IRDA_RXD " "Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[0\] " "Can't reserve pin KEY\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[1\] " "Can't reserve pin KEY\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[2\] " "Can't reserve pin KEY\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[3\] " "Can't reserve pin KEY\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "OTG_INT " "Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SD_WP_N " "Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SMA_CLKIN " "Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[0\] " "Can't reserve pin SW\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[0\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[0\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[10\] " "Can't reserve pin SW\[10\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[11\] " "Can't reserve pin SW\[11\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[12\] " "Can't reserve pin SW\[12\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[13\] " "Can't reserve pin SW\[13\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[14\] " "Can't reserve pin SW\[14\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[15\] " "Can't reserve pin SW\[15\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[16\] " "Can't reserve pin SW\[16\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[17\] " "Can't reserve pin SW\[17\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[1\] " "Can't reserve pin SW\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[1\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[1\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 13 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[2\] " "Can't reserve pin SW\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[2\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[2\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[3\] " "Can't reserve pin SW\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[3\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[3\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[4\] " "Can't reserve pin SW\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[4\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[4\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[5\] " "Can't reserve pin SW\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[5\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[5\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[6\] " "Can't reserve pin SW\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[6\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[6\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[7\] " "Can't reserve pin SW\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[7\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[7\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[8\] " "Can't reserve pin SW\[8\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[9\] " "Can't reserve pin SW\[9\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_CLK27 " "Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[0\] " "Can't reserve pin TD_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[1\] " "Can't reserve pin TD_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[2\] " "Can't reserve pin TD_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[3\] " "Can't reserve pin TD_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[4\] " "Can't reserve pin TD_DATA\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[5\] " "Can't reserve pin TD_DATA\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[6\] " "Can't reserve pin TD_DATA\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[7\] " "Can't reserve pin TD_DATA\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_HS " "Can't reserve pin TD_HS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_VS " "Can't reserve pin TD_VS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RTS " "Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RXD " "Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 645 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 647 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 649 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 651 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678212356274 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678212356283 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678212357060 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678212357061 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678212357061 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678212357061 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678212357062 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678212357062 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678212357063 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678212357067 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678212357067 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678212357067 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678212357068 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678212357068 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678212357069 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678212357069 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678212357069 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678212357069 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678212357069 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678212357069 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212357129 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678212357135 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678212358762 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212358856 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678212358888 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678212359068 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212359068 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678212359312 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678212361389 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678212361389 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678212361492 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678212361492 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678212361492 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212361494 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678212361579 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678212361584 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678212361775 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678212361775 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678212361944 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212362197 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678212362388 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "25 Cyclone IV E " "25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D2 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 15 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK2_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK3_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET0_LINK100 3.3-V LVTTL C14 " "Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET0_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET1_LINK100 3.3-V LVTTL D13 " "Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET1_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 113 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678212362443 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 534 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1155 " "Peak virtual memory: 1155 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:02 2023 " "Processing ended: Tue Mar 7 18:06:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678212362604 ""}