21 lines
633 B
VHDL
21 lines
633 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity Cmp4 is
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port(
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input0 : in std_logic_vector(3 downto 0);
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input1 : in std_logic_vector(3 downto 0);
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equal : out std_logic;
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notEqual : out std_logic;
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ltSigned : out std_logic;
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ltUnsigned : out std_logic);
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end Cmp4;
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architecture Behavioral of Cmp4 is
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begin
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equal <= '1' when (input0 = input1) else '0';
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notEqual <= '1' when (input0 /= input1) else '0';
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ltSigned <= '1' when (signed(input0) < signed(input1)) else '0';
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ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0';
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end Behavioral;
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