33 lines
2.2 KiB
Plaintext
33 lines
2.2 KiB
Plaintext
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vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
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design_name = hard_block
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design_name = AdderDemo
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instance = comp, \LEDR[4]~output\, LEDR[4]~output, AdderDemo, 1
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instance = comp, \LEDR[3]~output\, LEDR[3]~output, AdderDemo, 1
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instance = comp, \LEDR[2]~output\, LEDR[2]~output, AdderDemo, 1
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instance = comp, \LEDR[1]~output\, LEDR[1]~output, AdderDemo, 1
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instance = comp, \LEDR[0]~output\, LEDR[0]~output, AdderDemo, 1
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instance = comp, \SW[0]~input\, SW[0]~input, AdderDemo, 1
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instance = comp, \SW[1]~input\, SW[1]~input, AdderDemo, 1
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instance = comp, \SW[5]~input\, SW[5]~input, AdderDemo, 1
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instance = comp, \SW[4]~input\, SW[4]~input, AdderDemo, 1
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instance = comp, \Adder4Demo|bit1|cout~0\, Adder4Demo|bit1|cout~0, AdderDemo, 1
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instance = comp, \SW[6]~input\, SW[6]~input, AdderDemo, 1
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instance = comp, \SW[2]~input\, SW[2]~input, AdderDemo, 1
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instance = comp, \Adder4Demo|bit2|cout~0\, Adder4Demo|bit2|cout~0, AdderDemo, 1
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instance = comp, \SW[3]~input\, SW[3]~input, AdderDemo, 1
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instance = comp, \SW[7]~input\, SW[7]~input, AdderDemo, 1
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instance = comp, \Adder4Demo|bit3|cout~0\, Adder4Demo|bit3|cout~0, AdderDemo, 1
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instance = comp, \Adder4Demo|bit3|s\, Adder4Demo|bit3|s, AdderDemo, 1
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instance = comp, \Adder4Demo|bit2|s~0\, Adder4Demo|bit2|s~0, AdderDemo, 1
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instance = comp, \Adder4Demo|bit1|s~0\, Adder4Demo|bit1|s~0, AdderDemo, 1
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instance = comp, \Adder4Demo|bit0|s~0\, Adder4Demo|bit0|s~0, AdderDemo, 1
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