44 lines
2.0 KiB
Plaintext
44 lines
2.0 KiB
Plaintext
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--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=4 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
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--VERSION_BEGIN 20.1 cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_abs 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_divide 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION sign_div_unsign_7kh (denominator[3..0], numerator[3..0])
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RETURNS ( quotient[3..0], remainder[3..0]);
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--synthesis_resources = lut 9
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SUBDESIGN lpm_divide_i9m
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(
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denom[3..0] : input;
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numer[3..0] : input;
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quotient[3..0] : output;
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remain[3..0] : output;
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)
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VARIABLE
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divider : sign_div_unsign_7kh;
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numer_tmp[3..0] : WIRE;
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BEGIN
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divider.denominator[] = denom[];
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divider.numerator[] = numer_tmp[];
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numer_tmp[] = numer[];
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quotient[] = divider.quotient[];
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remain[] = divider.remainder[];
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END;
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--VALID FILE
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