636 lines
17 KiB
Plaintext
636 lines
17 KiB
Plaintext
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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-- DATE "11/18/2022 14:55:36"
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--
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-- Device: Altera EP4CE6E22C6 Package TQFP144
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY hard_block IS
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic
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);
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END hard_block;
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-- Design Ports Information
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-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
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ARCHITECTURE structure OF hard_block IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
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BEGIN
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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END structure;
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY Mux16_1 IS
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PORT (
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pin_name1 : OUT std_logic;
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Sel4 : IN std_logic;
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Sel3 : IN std_logic;
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Sel2 : IN std_logic;
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Sel1 : IN std_logic;
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I0 : IN std_logic;
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ze : IN std_logic;
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I2 : IN std_logic;
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I3 : IN std_logic;
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I4 : IN std_logic;
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I5 : IN std_logic;
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I6 : IN std_logic;
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I7 : IN std_logic;
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I8 : IN std_logic;
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I9 : IN std_logic;
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I10 : IN std_logic;
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I11 : IN std_logic;
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I12 : IN std_logic;
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I13 : IN std_logic;
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I14 : IN std_logic;
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I15 : IN std_logic
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);
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END Mux16_1;
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-- Design Ports Information
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-- pin_name1 => Location: PIN_76, I/O Standard: 2.5 V, Current Strength: Default
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-- I10 => Location: PIN_46, I/O Standard: 2.5 V, Current Strength: Default
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-- Sel2 => Location: PIN_80, I/O Standard: 2.5 V, Current Strength: Default
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-- I9 => Location: PIN_65, I/O Standard: 2.5 V, Current Strength: Default
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-- Sel1 => Location: PIN_112, I/O Standard: 2.5 V, Current Strength: Default
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-- I8 => Location: PIN_68, I/O Standard: 2.5 V, Current Strength: Default
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-- I11 => Location: PIN_87, I/O Standard: 2.5 V, Current Strength: Default
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-- Sel4 => Location: PIN_121, I/O Standard: 2.5 V, Current Strength: Default
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-- I5 => Location: PIN_85, I/O Standard: 2.5 V, Current Strength: Default
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-- I6 => Location: PIN_86, I/O Standard: 2.5 V, Current Strength: Default
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-- I4 => Location: PIN_69, I/O Standard: 2.5 V, Current Strength: Default
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-- I7 => Location: PIN_88, I/O Standard: 2.5 V, Current Strength: Default
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-- Sel3 => Location: PIN_89, I/O Standard: 2.5 V, Current Strength: Default
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-- I2 => Location: PIN_74, I/O Standard: 2.5 V, Current Strength: Default
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-- ze => Location: PIN_90, I/O Standard: 2.5 V, Current Strength: Default
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-- I0 => Location: PIN_91, I/O Standard: 2.5 V, Current Strength: Default
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-- I3 => Location: PIN_84, I/O Standard: 2.5 V, Current Strength: Default
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-- I13 => Location: PIN_66, I/O Standard: 2.5 V, Current Strength: Default
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-- I14 => Location: PIN_120, I/O Standard: 2.5 V, Current Strength: Default
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-- I12 => Location: PIN_83, I/O Standard: 2.5 V, Current Strength: Default
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-- I15 => Location: PIN_77, I/O Standard: 2.5 V, Current Strength: Default
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ARCHITECTURE structure OF Mux16_1 IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_pin_name1 : std_logic;
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SIGNAL ww_Sel4 : std_logic;
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SIGNAL ww_Sel3 : std_logic;
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SIGNAL ww_Sel2 : std_logic;
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SIGNAL ww_Sel1 : std_logic;
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SIGNAL ww_I0 : std_logic;
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SIGNAL ww_ze : std_logic;
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SIGNAL ww_I2 : std_logic;
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SIGNAL ww_I3 : std_logic;
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SIGNAL ww_I4 : std_logic;
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SIGNAL ww_I5 : std_logic;
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SIGNAL ww_I6 : std_logic;
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SIGNAL ww_I7 : std_logic;
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SIGNAL ww_I8 : std_logic;
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SIGNAL ww_I9 : std_logic;
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SIGNAL ww_I10 : std_logic;
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SIGNAL ww_I11 : std_logic;
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SIGNAL ww_I12 : std_logic;
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SIGNAL ww_I13 : std_logic;
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SIGNAL ww_I14 : std_logic;
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SIGNAL ww_I15 : std_logic;
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SIGNAL \pin_name1~output_o\ : std_logic;
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SIGNAL \I14~input_o\ : std_logic;
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SIGNAL \Sel2~input_o\ : std_logic;
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SIGNAL \Sel1~input_o\ : std_logic;
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SIGNAL \I12~input_o\ : std_logic;
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SIGNAL \inst14|inst2~7_combout\ : std_logic;
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SIGNAL \I13~input_o\ : std_logic;
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SIGNAL \I15~input_o\ : std_logic;
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SIGNAL \inst14|inst2~8_combout\ : std_logic;
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SIGNAL \I5~input_o\ : std_logic;
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SIGNAL \I6~input_o\ : std_logic;
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SIGNAL \I4~input_o\ : std_logic;
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SIGNAL \inst14|inst2~2_combout\ : std_logic;
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SIGNAL \I7~input_o\ : std_logic;
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SIGNAL \inst14|inst2~3_combout\ : std_logic;
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SIGNAL \Sel4~input_o\ : std_logic;
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SIGNAL \Sel3~input_o\ : std_logic;
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SIGNAL \I2~input_o\ : std_logic;
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SIGNAL \ze~input_o\ : std_logic;
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SIGNAL \I0~input_o\ : std_logic;
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SIGNAL \inst14|inst2~4_combout\ : std_logic;
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SIGNAL \I3~input_o\ : std_logic;
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SIGNAL \inst14|inst2~5_combout\ : std_logic;
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SIGNAL \inst14|inst2~6_combout\ : std_logic;
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SIGNAL \I10~input_o\ : std_logic;
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SIGNAL \I8~input_o\ : std_logic;
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SIGNAL \I9~input_o\ : std_logic;
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SIGNAL \inst14|inst2~0_combout\ : std_logic;
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SIGNAL \I11~input_o\ : std_logic;
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SIGNAL \inst14|inst2~1_combout\ : std_logic;
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SIGNAL \inst14|inst2~9_combout\ : std_logic;
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COMPONENT hard_block
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic);
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END COMPONENT;
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BEGIN
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pin_name1 <= ww_pin_name1;
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ww_Sel4 <= Sel4;
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ww_Sel3 <= Sel3;
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ww_Sel2 <= Sel2;
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ww_Sel1 <= Sel1;
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ww_I0 <= I0;
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ww_ze <= ze;
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ww_I2 <= I2;
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ww_I3 <= I3;
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ww_I4 <= I4;
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ww_I5 <= I5;
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ww_I6 <= I6;
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ww_I7 <= I7;
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ww_I8 <= I8;
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ww_I9 <= I9;
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ww_I10 <= I10;
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ww_I11 <= I11;
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ww_I12 <= I12;
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ww_I13 <= I13;
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ww_I14 <= I14;
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ww_I15 <= I15;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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auto_generated_inst : hard_block
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PORT MAP (
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devoe => ww_devoe,
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devclrn => ww_devclrn,
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devpor => ww_devpor);
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-- Location: IOOBUF_X34_Y4_N23
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\pin_name1~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \inst14|inst2~9_combout\,
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devoe => ww_devoe,
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o => \pin_name1~output_o\);
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-- Location: IOIBUF_X23_Y24_N8
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\I14~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_I14,
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o => \I14~input_o\);
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-- Location: IOIBUF_X34_Y7_N8
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\Sel2~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_Sel2,
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o => \Sel2~input_o\);
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-- Location: IOIBUF_X28_Y24_N1
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\Sel1~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_Sel1,
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o => \Sel1~input_o\);
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-- Location: IOIBUF_X34_Y9_N22
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\I12~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_I12,
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o => \I12~input_o\);
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-- Location: LCCOMB_X28_Y8_N12
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\inst14|inst2~7\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst14|inst2~7_combout\ = (\Sel2~input_o\ & ((\I14~input_o\) # ((\Sel1~input_o\)))) # (!\Sel2~input_o\ & (((!\Sel1~input_o\ & \I12~input_o\))))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1100101111001000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \I14~input_o\,
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datab => \Sel2~input_o\,
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datac => \Sel1~input_o\,
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datad => \I12~input_o\,
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combout => \inst14|inst2~7_combout\);
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-- Location: IOIBUF_X28_Y0_N1
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\I13~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_I13,
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o => \I13~input_o\);
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-- Location: IOIBUF_X34_Y4_N15
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\I15~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_I15,
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o => \I15~input_o\);
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-- Location: LCCOMB_X28_Y8_N6
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\inst14|inst2~8\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst14|inst2~8_combout\ = (\inst14|inst2~7_combout\ & (((\I15~input_o\)) # (!\Sel1~input_o\))) # (!\inst14|inst2~7_combout\ & (\Sel1~input_o\ & (\I13~input_o\)))
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||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1110101001100010",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \inst14|inst2~7_combout\,
|
||
|
|
datab => \Sel1~input_o\,
|
||
|
|
datac => \I13~input_o\,
|
||
|
|
datad => \I15~input_o\,
|
||
|
|
combout => \inst14|inst2~8_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y9_N8
|
||
|
|
\I5~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I5,
|
||
|
|
o => \I5~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y9_N1
|
||
|
|
\I6~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I6,
|
||
|
|
o => \I6~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X30_Y0_N1
|
||
|
|
\I4~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I4,
|
||
|
|
o => \I4~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N20
|
||
|
|
\inst14|inst2~2\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~2_combout\ = (\Sel1~input_o\ & (((\Sel2~input_o\)))) # (!\Sel1~input_o\ & ((\Sel2~input_o\ & (\I6~input_o\)) # (!\Sel2~input_o\ & ((\I4~input_o\)))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1111101000001100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \I6~input_o\,
|
||
|
|
datab => \I4~input_o\,
|
||
|
|
datac => \Sel1~input_o\,
|
||
|
|
datad => \Sel2~input_o\,
|
||
|
|
combout => \inst14|inst2~2_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y12_N22
|
||
|
|
\I7~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I7,
|
||
|
|
o => \I7~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N22
|
||
|
|
\inst14|inst2~3\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~3_combout\ = (\inst14|inst2~2_combout\ & (((\I7~input_o\) # (!\Sel1~input_o\)))) # (!\inst14|inst2~2_combout\ & (\I5~input_o\ & (\Sel1~input_o\)))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1110110000101100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \I5~input_o\,
|
||
|
|
datab => \inst14|inst2~2_combout\,
|
||
|
|
datac => \Sel1~input_o\,
|
||
|
|
datad => \I7~input_o\,
|
||
|
|
combout => \inst14|inst2~3_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X23_Y24_N15
|
||
|
|
\Sel4~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_Sel4,
|
||
|
|
o => \Sel4~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y12_N15
|
||
|
|
\Sel3~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_Sel3,
|
||
|
|
o => \Sel3~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y2_N15
|
||
|
|
\I2~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I2,
|
||
|
|
o => \I2~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y12_N8
|
||
|
|
\ze~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_ze,
|
||
|
|
o => \ze~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y12_N1
|
||
|
|
\I0~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I0,
|
||
|
|
o => \I0~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X33_Y8_N8
|
||
|
|
\inst14|inst2~4\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~4_combout\ = (\Sel2~input_o\ & (((\Sel1~input_o\)))) # (!\Sel2~input_o\ & ((\Sel1~input_o\ & (\ze~input_o\)) # (!\Sel1~input_o\ & ((\I0~input_o\)))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1110001111100000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \ze~input_o\,
|
||
|
|
datab => \Sel2~input_o\,
|
||
|
|
datac => \Sel1~input_o\,
|
||
|
|
datad => \I0~input_o\,
|
||
|
|
combout => \inst14|inst2~4_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y9_N15
|
||
|
|
\I3~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I3,
|
||
|
|
o => \I3~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N24
|
||
|
|
\inst14|inst2~5\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~5_combout\ = (\Sel2~input_o\ & ((\inst14|inst2~4_combout\ & ((\I3~input_o\))) # (!\inst14|inst2~4_combout\ & (\I2~input_o\)))) # (!\Sel2~input_o\ & (((\inst14|inst2~4_combout\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1111100000111000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \I2~input_o\,
|
||
|
|
datab => \Sel2~input_o\,
|
||
|
|
datac => \inst14|inst2~4_combout\,
|
||
|
|
datad => \I3~input_o\,
|
||
|
|
combout => \inst14|inst2~5_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N18
|
||
|
|
\inst14|inst2~6\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~6_combout\ = (\Sel4~input_o\ & (((\Sel3~input_o\)))) # (!\Sel4~input_o\ & ((\Sel3~input_o\ & (\inst14|inst2~3_combout\)) # (!\Sel3~input_o\ & ((\inst14|inst2~5_combout\)))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1110001111100000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \inst14|inst2~3_combout\,
|
||
|
|
datab => \Sel4~input_o\,
|
||
|
|
datac => \Sel3~input_o\,
|
||
|
|
datad => \inst14|inst2~5_combout\,
|
||
|
|
combout => \inst14|inst2~6_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X7_Y0_N1
|
||
|
|
\I10~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I10,
|
||
|
|
o => \I10~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X30_Y0_N8
|
||
|
|
\I8~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I8,
|
||
|
|
o => \I8~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X28_Y0_N22
|
||
|
|
\I9~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I9,
|
||
|
|
o => \I9~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N0
|
||
|
|
\inst14|inst2~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~0_combout\ = (\Sel1~input_o\ & (((\I9~input_o\) # (\Sel2~input_o\)))) # (!\Sel1~input_o\ & (\I8~input_o\ & ((!\Sel2~input_o\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1100110011100010",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \I8~input_o\,
|
||
|
|
datab => \Sel1~input_o\,
|
||
|
|
datac => \I9~input_o\,
|
||
|
|
datad => \Sel2~input_o\,
|
||
|
|
combout => \inst14|inst2~0_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X34_Y10_N8
|
||
|
|
\I11~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_I11,
|
||
|
|
o => \I11~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N10
|
||
|
|
\inst14|inst2~1\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~1_combout\ = (\inst14|inst2~0_combout\ & (((\I11~input_o\) # (!\Sel2~input_o\)))) # (!\inst14|inst2~0_combout\ & (\I10~input_o\ & ((\Sel2~input_o\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1110001011001100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \I10~input_o\,
|
||
|
|
datab => \inst14|inst2~0_combout\,
|
||
|
|
datac => \I11~input_o\,
|
||
|
|
datad => \Sel2~input_o\,
|
||
|
|
combout => \inst14|inst2~1_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X28_Y8_N8
|
||
|
|
\inst14|inst2~9\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst14|inst2~9_combout\ = (\inst14|inst2~6_combout\ & ((\inst14|inst2~8_combout\) # ((!\Sel4~input_o\)))) # (!\inst14|inst2~6_combout\ & (((\Sel4~input_o\ & \inst14|inst2~1_combout\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1011110010001100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \inst14|inst2~8_combout\,
|
||
|
|
datab => \inst14|inst2~6_combout\,
|
||
|
|
datac => \Sel4~input_o\,
|
||
|
|
datad => \inst14|inst2~1_combout\,
|
||
|
|
combout => \inst14|inst2~9_combout\);
|
||
|
|
|
||
|
|
ww_pin_name1 <= \pin_name1~output_o\;
|
||
|
|
END structure;
|
||
|
|
|
||
|
|
|