133 lines
8.9 KiB
Plaintext
133 lines
8.9 KiB
Plaintext
|
Flow report for MuxDemo
|
||
|
Thu Dec 1 18:12:53 2022
|
||
|
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||
|
|
||
|
|
||
|
---------------------
|
||
|
; Table of Contents ;
|
||
|
---------------------
|
||
|
1. Legal Notice
|
||
|
2. Flow Summary
|
||
|
3. Flow Settings
|
||
|
4. Flow Non-Default Global Settings
|
||
|
5. Flow Elapsed Time
|
||
|
6. Flow OS Summary
|
||
|
7. Flow Log
|
||
|
8. Flow Messages
|
||
|
9. Flow Suppressed Messages
|
||
|
|
||
|
|
||
|
|
||
|
----------------
|
||
|
; Legal Notice ;
|
||
|
----------------
|
||
|
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
and other software and tools, and any partner logic
|
||
|
functions, and any output files from any of the foregoing
|
||
|
(including device programming or simulation files), and any
|
||
|
associated documentation or information are expressly subject
|
||
|
to the terms and conditions of the Intel Program License
|
||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||
|
agreement, including, without limitation, that your use is for
|
||
|
the sole purpose of programming logic devices manufactured by
|
||
|
Intel and sold by Intel or its authorized distributors. Please
|
||
|
refer to the applicable agreement for further details, at
|
||
|
https://fpgasoftware.intel.com/eula.
|
||
|
|
||
|
|
||
|
|
||
|
+----------------------------------------------------------------------------------+
|
||
|
; Flow Summary ;
|
||
|
+------------------------------------+---------------------------------------------+
|
||
|
; Flow Status ; Successful - Thu Dec 1 18:12:53 2022 ;
|
||
|
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||
|
; Revision Name ; MuxDemo ;
|
||
|
; Top-level Entity Name ; Mux16_1 ;
|
||
|
; Family ; Cyclone IV E ;
|
||
|
; Total logic elements ; 10 / 6,272 ( < 1 % ) ;
|
||
|
; Total combinational functions ; 10 / 6,272 ( < 1 % ) ;
|
||
|
; Dedicated logic registers ; 0 / 6,272 ( 0 % ) ;
|
||
|
; Total registers ; 0 ;
|
||
|
; Total pins ; 21 / 92 ( 23 % ) ;
|
||
|
; Total virtual pins ; 0 ;
|
||
|
; Total memory bits ; 0 / 276,480 ( 0 % ) ;
|
||
|
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
|
||
|
; Total PLLs ; 0 / 2 ( 0 % ) ;
|
||
|
; Device ; EP4CE6E22C6 ;
|
||
|
; Timing Models ; Final ;
|
||
|
+------------------------------------+---------------------------------------------+
|
||
|
|
||
|
|
||
|
+-----------------------------------------+
|
||
|
; Flow Settings ;
|
||
|
+-------------------+---------------------+
|
||
|
; Option ; Setting ;
|
||
|
+-------------------+---------------------+
|
||
|
; Start date & time ; 12/01/2022 18:12:42 ;
|
||
|
; Main task ; Compilation ;
|
||
|
; Revision Name ; MuxDemo ;
|
||
|
+-------------------+---------------------+
|
||
|
|
||
|
|
||
|
+------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
; Flow Non-Default Global Settings ;
|
||
|
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||
|
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||
|
; COMPILER_SIGNATURE_ID ; 198516037997543.166991836238102 ; -- ; -- ; -- ;
|
||
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
|
||
|
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
|
||
|
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
|
||
|
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
||
|
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ;
|
||
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ;
|
||
|
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ;
|
||
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||
|
; TOP_LEVEL_ENTITY ; Mux16_1 ; MuxDemo ; -- ; -- ;
|
||
|
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||
|
|
||
|
|
||
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||
|
; Flow Elapsed Time ;
|
||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 395 MB ; 00:00:13 ;
|
||
|
; Fitter ; 00:00:02 ; 1.0 ; 937 MB ; 00:00:02 ;
|
||
|
; Assembler ; 00:00:01 ; 1.0 ; 353 MB ; 00:00:00 ;
|
||
|
; Timing Analyzer ; 00:00:01 ; 1.0 ; 465 MB ; 00:00:01 ;
|
||
|
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 600 MB ; 00:00:00 ;
|
||
|
; Total ; 00:00:09 ; -- ; -- ; 00:00:16 ;
|
||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||
|
|
||
|
|
||
|
+----------------------------------------------------------------------------------------+
|
||
|
; Flow OS Summary ;
|
||
|
+----------------------+------------------+----------------+------------+----------------+
|
||
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||
|
+----------------------+------------------+----------------+------------+----------------+
|
||
|
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
|
||
|
; Fitter ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
|
||
|
; Assembler ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
|
||
|
; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
|
||
|
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
|
||
|
+----------------------+------------------+----------------+------------+----------------+
|
||
|
|
||
|
|
||
|
------------
|
||
|
; Flow Log ;
|
||
|
------------
|
||
|
quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo
|
||
|
quartus_fit --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
|
||
|
quartus_asm --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
|
||
|
quartus_sta MuxDemo -c MuxDemo
|
||
|
quartus_eda --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
|
||
|
|
||
|
|
||
|
|