2023-03-07 19:02:31 +00:00
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vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf
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2023-03-07 20:59:22 +00:00
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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2023-03-07 19:02:31 +00:00
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
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design_name = hard_block
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design_name = EqCmpDemo
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instance = comp, \LEDG[0]~output\, LEDG[0]~output, EqCmpDemo, 1
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instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1
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instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1
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instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1
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instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1
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2023-03-07 20:59:22 +00:00
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instance = comp, \inst1|inst~0\, inst1|inst~0, EqCmpDemo, 1
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2023-03-07 19:02:31 +00:00
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instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1
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instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1
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instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1
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instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1
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2023-03-07 20:59:22 +00:00
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instance = comp, \inst1|inst~1\, inst1|inst~1, EqCmpDemo, 1
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instance = comp, \inst1|inst\, inst1|inst, EqCmpDemo, 1
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