82 lines
1.5 KiB
VHDL
82 lines
1.5 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity ControlUnit is
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port(reset : in std_logic;
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clk : in std_logic;
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statop : in std_logic;
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laprst : in std_logic;
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cntRst : out std_logic;
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cntEnb : out std_logic;
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regEnb : out std_logic);
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end ControlUnit;
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architecture Behavioral of ControlUnit is
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type TState is (CLEARED, STARTED, STOPPED, LAPVIEW);
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signal s_currentState, s_nextState : TState;
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begin
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sync_proc : process(clk)
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begin
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if (rising_edge(clk)) then
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if (reset = '1') then
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s_currentState <= CLEARED;
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else
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s_currentState <= s_nextState;
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end if;
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end if;
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end process;
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comb_proc : process(s_currentState, statop, laprst)
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begin
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case (s_currentState) is
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when CLEARED =>
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cntRst <= '1';
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cntEnb <= '1';
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regEnb <= '1';
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if (statop = '1') then
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s_nextState <= STARTED;
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else
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s_nextState <= CLEARED;
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end if;
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when STARTED =>
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cntRst <= '0';
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cntEnb <= '1';
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regEnb <= '1';
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if (laprst = '1') then
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s_nextState <= LAPVIEW;
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elsif (statop = '1') then
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s_nextState <= STOPPED;
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else
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s_nextState <= STARTED;
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end if;
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when STOPPED =>
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cntRst <= '0';
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cntEnb <= '0';
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regEnb <= '1';
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if (statop = '1') then
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s_nextState <= STARTED;
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elsif (laprst = '1') then
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s_nextState <= CLEARED;
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else
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s_nextState <= STOPPED;
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end if;
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when LAPVIEW =>
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cntRst <= '0';
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cntEnb <= '1';
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regEnb <= '0';
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if (laprst = '1') then
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s_nextState <= STARTED;
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else
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s_nextState <= LAPVIEW;
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end if;
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end case;
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end process;
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end Behavioral;
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