17 lines
375 B
VHDL
17 lines
375 B
VHDL
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-- Bibliotecas
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Interface (portos)
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entity AND2Gate is
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port(
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inPort0 : in std_logic;
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inPort1 : in std_logic;
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outPort : out std_logic
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);
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end AND2Gate;
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-- Implementação (descrição do funcionalidade)
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architecture Behavioral of AND2Gate is begin
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outPort <= inPort0 and inPort1;
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end Behavioral;
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