40 lines
872 B
VHDL
40 lines
872 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity TimerN is
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generic (N : positive := 6);
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port
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(
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clk : in std_logic;
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enable : in std_logic;
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start : in std_logic;
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reset : in std_logic;
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timerOut : out std_logic
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);
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end TimerN;
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architecture Behavioral of TimerN is
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signal s_count : std_logic_vector(31 downto 0);
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begin
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process (clk)
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begin
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if (rising_edge(clk)) then
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if (reset = '0' and enable = '1') then
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if (unsigned(s_count) < N and not (unsigned(s_count) = 0 and start = '0')) then
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s_count <= std_logic_vector(unsigned(s_count) + 1);
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else
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s_count <= (others => '0');
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end if;
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elsif (reset = '1') then
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s_count <= (others => '0');
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end if;
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if (unsigned(s_count) = 0) then
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timerOut <= '0';
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else
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timerOut <= '1';
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end if;
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end if;
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end process;
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end Behavioral;
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