79 lines
1.5 KiB
VHDL
79 lines
1.5 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity CounterDemo is
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port
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(
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CLOCK_50 : in std_logic;
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KEY : in std_logic_vector(1 downto 0);
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HEX0 : out std_logic_vector(6 downto 0);
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HEX1 : out std_logic_vector(6 downto 0)
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);
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end CounterDemo;
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architecture Shell of CounterDemo is
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signal s_pulse, s_reset, s_toggle : std_logic;
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signal s_count : std_logic_vector(3 downto 0);
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signal s_startStop : std_logic := '1';
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signal s_display0, s_display1 : std_logic_vector(3 downto 0);
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begin
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s_reset <= not KEY(1);
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pulse_gen : entity work.pulse_gen(Behavioral)
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generic map (MAX => 20_000_000)
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port map
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(
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clk => CLOCK_50,
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pulse => s_pulse
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);
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key_debounce : entity work.Debouncer(Behavioral)
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port map
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(
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refClk => CLOCK_50,
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dirtyIn => KEY(0),
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pulsedOut => s_toggle
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);
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start_stop : entity work.ToggleSwitch(Behavioral)
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port map
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(
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toggle => s_toggle,
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reset => s_reset,
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startStop => s_startStop
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);
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counter : entity work.Counter(Behavioral)
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port map
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(
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clk => s_pulse,
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reset => s_reset,
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start => s_startStop,
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count => s_count
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);
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bin2bcd : entity work.Bin2Bcd(Behavioral)
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port map
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(
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hexIn => s_count,
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decOut0 => s_display0,
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decOut1 => s_display1
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);
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display0 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display0,
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decOut_n => HEX0
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);
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display1 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display1,
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decOut_n => HEX1
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);
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end Shell;
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