93 lines
2.4 KiB
Plaintext
93 lines
2.4 KiB
Plaintext
|
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
|
// Your use of Intel Corporation's design tools, logic functions
|
||
|
|
// and other software and tools, and any partner logic
|
||
|
|
// functions, and any output files from any of the foregoing
|
||
|
|
// (including device programming or simulation files), and any
|
||
|
|
// associated documentation or information are expressly subject
|
||
|
|
// to the terms and conditions of the Intel Program License
|
||
|
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
// the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
// agreement, including, without limitation, that your use is for
|
||
|
|
// the sole purpose of programming logic devices manufactured by
|
||
|
|
// Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
// refer to the applicable agreement for further details, at
|
||
|
|
// https://fpgasoftware.intel.com/eula.
|
||
|
|
|
||
|
|
// *****************************************************************************
|
||
|
|
// This file contains a Verilog test bench with test vectors .The test vectors
|
||
|
|
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||
|
|
// the top level entity of the current Quartus project .The user can use this
|
||
|
|
// testbench to simulate his design using a third-party simulation tool .
|
||
|
|
// *****************************************************************************
|
||
|
|
// Generated on "11/04/2022 15:15:39"
|
||
|
|
|
||
|
|
// Verilog Test Bench (with test vectors) for design : Dec2_4
|
||
|
|
//
|
||
|
|
// Simulation tool : 3rd Party
|
||
|
|
//
|
||
|
|
|
||
|
|
`timescale 1 ps/ 1 ps
|
||
|
|
module Dec2_4_vlg_vec_tst();
|
||
|
|
// constants
|
||
|
|
// general purpose registers
|
||
|
|
reg E0L;
|
||
|
|
reg E1;
|
||
|
|
reg X0;
|
||
|
|
reg X1;
|
||
|
|
// wires
|
||
|
|
wire Y0;
|
||
|
|
wire Y1;
|
||
|
|
wire Y2;
|
||
|
|
wire Y3;
|
||
|
|
|
||
|
|
// assign statements (if any)
|
||
|
|
Dec2_4 i1 (
|
||
|
|
// port map - connection between master ports and signals/registers
|
||
|
|
.E0L(E0L),
|
||
|
|
.E1(E1),
|
||
|
|
.X0(X0),
|
||
|
|
.X1(X1),
|
||
|
|
.Y0(Y0),
|
||
|
|
.Y1(Y1),
|
||
|
|
.Y2(Y2),
|
||
|
|
.Y3(Y3)
|
||
|
|
);
|
||
|
|
initial
|
||
|
|
begin
|
||
|
|
#1000000 $finish;
|
||
|
|
end
|
||
|
|
|
||
|
|
// E0L
|
||
|
|
always
|
||
|
|
begin
|
||
|
|
E0L = 1'b0;
|
||
|
|
E0L = #100000 1'b1;
|
||
|
|
#100000;
|
||
|
|
end
|
||
|
|
|
||
|
|
// E1
|
||
|
|
always
|
||
|
|
begin
|
||
|
|
E1 = 1'b0;
|
||
|
|
E1 = #50000 1'b1;
|
||
|
|
#50000;
|
||
|
|
end
|
||
|
|
|
||
|
|
// X1
|
||
|
|
always
|
||
|
|
begin
|
||
|
|
X1 = 1'b0;
|
||
|
|
X1 = #25000 1'b1;
|
||
|
|
#25000;
|
||
|
|
end
|
||
|
|
|
||
|
|
// X0
|
||
|
|
always
|
||
|
|
begin
|
||
|
|
X0 = 1'b0;
|
||
|
|
X0 = #12500 1'b1;
|
||
|
|
#12500;
|
||
|
|
end
|
||
|
|
endmodule
|
||
|
|
|