38 lines
768 B
VHDL
38 lines
768 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity AccN is
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generic ( N : positive := 8 );
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port (
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dataIn : in std_logic_vector((N-1) downto 0);
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reset, enable, clk : std_logic;
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dataOut : out std_logic_vector((N-1) downto 0)
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);
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end AccN;
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architecture Behavioral of AccN is
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signal s_adderOut : std_logic_vector((N-1) downto 0);
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signal s_regOut : std_logic_vector((N-1) downto 0);
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begin
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adder : entity work.AdderN(Behavioral)
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generic map ( N => N )
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port map
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(
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operand1 => dataIn,
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operand2 => s_regOut,
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result => s_adderOut
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);
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reg : entity work.RegN(Behavioral)
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generic map ( N => N )
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port map
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(
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dataIn => s_adderOut,
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reset => reset, enable => enable, clk => clk,
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dataOut => s_regOut
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);
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dataOut <= s_regOut;
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end Behavioral;
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