21 lines
299 B
VHDL
21 lines
299 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity FlipFlopD is
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port
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(
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clk : in std_logic;
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d : in std_logic;
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q : out std_logic;
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);
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end FlipFlopD;
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architecture Behav of FlipFlopD is
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begin
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process (clk)
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begin
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if (rising_edge(clk)) then
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q <= d;
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end if;
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end process;
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end Behav;
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