50 lines
1.2 KiB
VHDL
50 lines
1.2 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity CntBCDUp4 is
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port(reset : in std_logic;
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clk : in std_logic;
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enable1 : in std_logic;
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enable2 : in std_logic;
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count : out std_logic_vector(15 downto 0));
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end CntBCDUp4;
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architecture Behavioral of CntBCDUp4 is
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signal s_count : unsigned(15 downto 0);
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begin
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count_proc : process(clk)
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begin
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if (rising_edge(clk)) then
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if (reset = '1') then
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s_count <= (others => '0');
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elsif ((enable1 = '1') and (enable2 = '1')) then
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if (s_count(3 downto 0) = X"9") then
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s_count(3 downto 0) <= X"0";
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if (s_count(7 downto 4) = X"9") then
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s_count(7 downto 4) <= X"0";
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if (s_count(11 downto 8) = X"9") then
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s_count(11 downto 8) <= X"0";
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if (s_count(15 downto 12) = X"9") then
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s_count(15 downto 12) <= X"0";
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else
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s_count(15 downto 12) <= s_count(15 downto 12) + 1;
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end if;
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else
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s_count(11 downto 8) <= s_count(11 downto 8) + 1;
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end if;
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else
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s_count(7 downto 4) <= s_count(7 downto 4) + 1;
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end if;
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else
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s_count(3 downto 0) <= s_count(3 downto 0) + 1;
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end if;
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end if;
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end if;
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end process;
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count <= std_logic_vector(s_count);
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end Behavioral;
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