16 lines
284 B
VHDL
16 lines
284 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity FullAdder is
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port
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(
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a, b, cin : in std_logic;
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s, cout : out std_logic
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);
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end FullAdder;
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architecture Behavioral of FullAdder is
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begin
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s <= a xor b xor cin;
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cout <= (a and b) or (a and cin) or (b and cin);
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end Behavioral;
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