33 lines
856 B
VHDL
33 lines
856 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Adder4 is
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port
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(
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a, b : in std_logic_vector(3 downto 0);
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cin : in std_logic;
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s : out std_logic_vector(3 downto 0);
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cout : out std_logic
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);
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end Adder4;
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architecture Structural of Adder4 is
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signal intCarry : std_logic_vector(2 downto 0);
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begin
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bit0 : entity work.FullAdder(Behavioral) port map
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(
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a => a(0), b => b(0), cin => cin, s => s(0), cout => intCarry(0)
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);
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bit1 : entity work.FullAdder(Behavioral) port map
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(
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a => a(1), b => b(1), cin => intCarry(0), s => s(1), cout => intCarry(1)
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);
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bit2 : entity work.FullAdder(Behavioral) port map
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(
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a => a(2), b => b(2), cin => intCarry(1), s => s(2), cout => intCarry(2)
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);
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bit3 : entity work.FullAdder(Behavioral) port map
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(
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a => a(3), b => b(3), cin => intCarry(2), s => s(3), cout => cout
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);
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end Structural;
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