343 lines
7.0 KiB
Plaintext
343 lines
7.0 KiB
Plaintext
|
/*<simulation_settings>
|
||
|
|
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vht"</ftestbench_cmd>
|
||
|
|
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vht"</ttestbench_cmd>
|
||
|
|
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/" Dec2_4EnDemo -c Dec2_4EnDemo</fnetlist_cmd>
|
||
|
|
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/" Dec2_4EnDemo -c Dec2_4EnDemo</tnetlist_cmd>
|
||
|
|
<modelsim_script>onerror {exit -code 1}
|
||
|
|
vlib work
|
||
|
|
vcom -work work Dec2_4EnDemo.vho
|
||
|
|
vcom -work work Dec2_4En_1.vwf.vht
|
||
|
|
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
|
||
|
|
vcd file -direction Dec2_4EnDemo.msim.vcd
|
||
|
|
vcd add -internal Dec2_4En_vhd_vec_tst/*
|
||
|
|
vcd add -internal Dec2_4En_vhd_vec_tst/i1/*
|
||
|
|
proc simTimestamp {} {
|
||
|
|
echo "Simulation time: $::now ps"
|
||
|
|
if { [string equal running [runStatus]] } {
|
||
|
|
after 2500 simTimestamp
|
||
|
|
}
|
||
|
|
}
|
||
|
|
after 2500 simTimestamp
|
||
|
|
run -all
|
||
|
|
quit -f
|
||
|
|
</modelsim_script>
|
||
|
|
<modelsim_script_timing>onerror {exit -code 1}
|
||
|
|
vlib work
|
||
|
|
vcom -work work Dec2_4EnDemo.vho
|
||
|
|
vcom -work work Dec2_4En_1.vwf.vht
|
||
|
|
vsim -novopt -c -t 1ps -sdfmax Dec2_4En_vhd_vec_tst/i1=Dec2_4EnDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
|
||
|
|
vcd file -direction Dec2_4EnDemo.msim.vcd
|
||
|
|
vcd add -internal Dec2_4En_vhd_vec_tst/*
|
||
|
|
vcd add -internal Dec2_4En_vhd_vec_tst/i1/*
|
||
|
|
proc simTimestamp {} {
|
||
|
|
echo "Simulation time: $::now ps"
|
||
|
|
if { [string equal running [runStatus]] } {
|
||
|
|
after 2500 simTimestamp
|
||
|
|
}
|
||
|
|
}
|
||
|
|
after 2500 simTimestamp
|
||
|
|
run -all
|
||
|
|
quit -f
|
||
|
|
</modelsim_script_timing>
|
||
|
|
<hdl_lang>vhdl</hdl_lang>
|
||
|
|
</simulation_settings>*/
|
||
|
|
/*
|
||
|
|
WARNING: Do NOT edit the input and output ports in this file in a text
|
||
|
|
editor if you plan to continue editing the block that represents it in
|
||
|
|
the Block Editor! File corruption is VERY likely to occur.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
|
and other software and tools, and any partner logic
|
||
|
|
functions, and any output files from any of the foregoing
|
||
|
|
(including device programming or simulation files), and any
|
||
|
|
associated documentation or information are expressly subject
|
||
|
|
to the terms and conditions of the Intel Program License
|
||
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
agreement, including, without limitation, that your use is for
|
||
|
|
the sole purpose of programming logic devices manufactured by
|
||
|
|
Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
refer to the applicable agreement for further details, at
|
||
|
|
https://fpgasoftware.intel.com/eula.
|
||
|
|
*/
|
||
|
|
|
||
|
|
HEADER
|
||
|
|
{
|
||
|
|
VERSION = 1;
|
||
|
|
TIME_UNIT = ns;
|
||
|
|
DATA_OFFSET = 0.0;
|
||
|
|
DATA_DURATION = 1000.0;
|
||
|
|
SIMULATION_TIME = 0.0;
|
||
|
|
GRID_PHASE = 0.0;
|
||
|
|
GRID_PERIOD = 10.0;
|
||
|
|
GRID_DUTY_CYCLE = 50;
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("enable")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = INPUT;
|
||
|
|
PARENT = "";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("inputs")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = BUS;
|
||
|
|
WIDTH = 2;
|
||
|
|
LSB_INDEX = 0;
|
||
|
|
DIRECTION = INPUT;
|
||
|
|
PARENT = "";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("inputs[1]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = INPUT;
|
||
|
|
PARENT = "inputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("inputs[0]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = INPUT;
|
||
|
|
PARENT = "inputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("outputs")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = BUS;
|
||
|
|
WIDTH = 4;
|
||
|
|
LSB_INDEX = 0;
|
||
|
|
DIRECTION = OUTPUT;
|
||
|
|
PARENT = "";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("outputs[3]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = OUTPUT;
|
||
|
|
PARENT = "outputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("outputs[2]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = OUTPUT;
|
||
|
|
PARENT = "outputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("outputs[1]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = OUTPUT;
|
||
|
|
PARENT = "outputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
SIGNAL("outputs[0]")
|
||
|
|
{
|
||
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
||
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
||
|
|
WIDTH = 1;
|
||
|
|
LSB_INDEX = -1;
|
||
|
|
DIRECTION = OUTPUT;
|
||
|
|
PARENT = "outputs";
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("enable")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 12;
|
||
|
|
LEVEL 0 FOR 40.0;
|
||
|
|
LEVEL 1 FOR 40.0;
|
||
|
|
}
|
||
|
|
LEVEL 0 FOR 40.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("inputs[1]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 25;
|
||
|
|
LEVEL 0 FOR 20.0;
|
||
|
|
LEVEL 1 FOR 20.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("inputs[0]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 50;
|
||
|
|
LEVEL 0 FOR 10.0;
|
||
|
|
LEVEL 1 FOR 10.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("outputs[3]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
LEVEL X FOR 1000.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("outputs[2]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
LEVEL X FOR 1000.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("outputs[1]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
LEVEL X FOR 1000.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
TRANSITION_LIST("outputs[0]")
|
||
|
|
{
|
||
|
|
NODE
|
||
|
|
{
|
||
|
|
REPEAT = 1;
|
||
|
|
LEVEL X FOR 1000.0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "enable";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 0;
|
||
|
|
TREE_LEVEL = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "inputs";
|
||
|
|
EXPAND_STATUS = EXPANDED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 1;
|
||
|
|
TREE_LEVEL = 0;
|
||
|
|
CHILDREN = 2, 3;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "inputs[1]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 2;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "inputs[0]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 3;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "outputs";
|
||
|
|
EXPAND_STATUS = EXPANDED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 4;
|
||
|
|
TREE_LEVEL = 0;
|
||
|
|
CHILDREN = 5, 6, 7, 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "outputs[3]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 5;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "outputs[2]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 6;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "outputs[1]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 7;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
DISPLAY_LINE
|
||
|
|
{
|
||
|
|
CHANNEL = "outputs[0]";
|
||
|
|
EXPAND_STATUS = COLLAPSED;
|
||
|
|
RADIX = Binary;
|
||
|
|
TREE_INDEX = 8;
|
||
|
|
TREE_LEVEL = 1;
|
||
|
|
PARENT = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
TIME_BAR
|
||
|
|
{
|
||
|
|
TIME = 0;
|
||
|
|
MASTER = TRUE;
|
||
|
|
}
|
||
|
|
;
|