47 lines
1.1 KiB
VHDL
47 lines
1.1 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Dec2_4En is
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port (
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enable : in std_logic;
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inputs : in std_logic_vector(1 downto 0);
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outputs : out std_logic_vector(3 downto 0)
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);
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end Dec2_4En;
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architecture BehavEquations of Dec2_4En is
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begin
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outputs(0) <= enable and (not inputs(1)) and (not inputs(0));
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outputs(1) <= enable and (not inputs(1)) and ( inputs(0));
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outputs(2) <= enable and ( inputs(1)) and (not inputs(0));
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outputs(3) <= enable and ( inputs(1)) and ( inputs(0));
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end BehavEquations;
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architecture BehavAssign of Dec2_4En is
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begin
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outputs <= "0000" when (enable = '0') else
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"0001" when (inputs = "00") else
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"0010" when (inputs = "01") else
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"0100" when (inputs = "10") else
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"1000";
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end BehavAssign;
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architecture BehavProc of Dec2_4En is
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begin
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process(enable, inputs)
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begin
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if (enable = '0') then
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outputs <= "0000";
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else
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if (inputs = "00") then
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outputs <= "0001";
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elsif (inputs = "01") then
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outputs <= "0010";
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elsif (inputs = "10") then
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outputs <= "0100";
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else
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outputs <= "1000";
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end if;
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end if;
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end process;
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end BehavProc;
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