24 lines
383 B
VHDL
24 lines
383 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Mux2_1 is
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port
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(
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dataIn0 : in std_logic;
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dataIn1 : in std_logic;
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sel : in std_logic;
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dataOut : out std_logic
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);
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end Mux2_1;
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architecture Behavioral of Mux2_1 is
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begin
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process(dataIn0, dataIn1, sel)
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begin
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if (sel = '0') then
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dataOut <= dataIn0;
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else
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dataOut <= dataIn1;
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end if;
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end process;
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end Behavioral;
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