14 lines
243 B
VHDL
14 lines
243 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity NOTGate is
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port (
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inPort : in std_logic;
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outPort : out std_logic
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);
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end NOTGate;
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architecture Behavioral of NOTGate is
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begin
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outPort <= not inPort;
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end Behavioral;
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